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elf.h

@@ -2,7 +2,7 @@
 // format of an ELF executable file
 //
 
-#define ELF_MAGIC 0x464C457FU	// "\x7FELF" in little endian
+#define ELF_MAGIC 0x464C457FU  // "\x7FELF" in little endian
 
 struct elfhdr {
   uint magic;  // must equal ELF_MAGIC
@@ -34,10 +34,10 @@ struct proghdr {
 };
 
 // Values for Proghdr type
-#define ELF_PROG_LOAD		1
+#define ELF_PROG_LOAD           1
 
 // Flag bits for Proghdr flags
-#define ELF_PROG_FLAG_EXEC	1
-#define ELF_PROG_FLAG_WRITE	2
-#define ELF_PROG_FLAG_READ	4
+#define ELF_PROG_FLAG_EXEC      1
+#define ELF_PROG_FLAG_WRITE     2
+#define ELF_PROG_FLAG_READ      4
 

ide.c

@@ -11,8 +11,8 @@
 
 #define IDE_BSY     0x80
 #define IDE_DRDY    0x40
-#define IDE_DF		0x20
-#define IDE_ERR		0x01
+#define IDE_DF      0x20
+#define IDE_ERR     0x01
 
 struct ide_request {
   int diskno;

lapic.c

@@ -7,84 +7,84 @@
 #include "mmu.h"
 #include "proc.h"
 
-enum {					// Local APIC registers
-  LAPIC_ID  = 0x0020,	// ID
-  LAPIC_VER = 0x0030,	// Version
-  LAPIC_TPR = 0x0080,	// Task Priority
-  LAPIC_APR = 0x0090,	// Arbitration Priority
-  LAPIC_PPR = 0x00A0,	// Processor Priority
-  LAPIC_EOI = 0x00B0,	// EOI
-  LAPIC_LDR = 0x00D0,	// Logical Destination
-  LAPIC_DFR = 0x00E0,	// Destination Format
-  LAPIC_SVR = 0x00F0,	// Spurious Interrupt Vector
-  LAPIC_ISR = 0x0100,	// Interrupt Status (8 registers)
-  LAPIC_TMR = 0x0180,	// Trigger Mode (8 registers)
-  LAPIC_IRR = 0x0200,	// Interrupt Request (8 registers)
-  LAPIC_ESR = 0x0280,	// Error Status
-  LAPIC_ICRLO = 0x0300,	// Interrupt Command
-  LAPIC_ICRHI = 0x0310,	// Interrupt Command [63:32]
-  LAPIC_TIMER = 0x0320,	// Local Vector Table 0 (TIMER)
-  LAPIC_PCINT = 0x0340,	// Performance Counter LVT
-  LAPIC_LINT0 = 0x0350,	// Local Vector Table 1 (LINT0)
-  LAPIC_LINT1 = 0x0360,	// Local Vector Table 2 (LINT1)
-  LAPIC_ERROR = 0x0370,	// Local Vector Table 3 (ERROR)
-  LAPIC_TICR = 0x0380,	// Timer Initial Count
-  LAPIC_TCCR = 0x0390,	// Timer Current Count
-  LAPIC_TDCR = 0x03E0,	// Timer Divide Configuration
+enum {  // Local APIC registers
+  LAPIC_ID  = 0x0020,   // ID
+  LAPIC_VER = 0x0030,   // Version
+  LAPIC_TPR = 0x0080,   // Task Priority
+  LAPIC_APR = 0x0090,   // Arbitration Priority
+  LAPIC_PPR = 0x00A0,   // Processor Priority
+  LAPIC_EOI = 0x00B0,   // EOI
+  LAPIC_LDR = 0x00D0,   // Logical Destination
+  LAPIC_DFR = 0x00E0,   // Destination Format
+  LAPIC_SVR = 0x00F0,   // Spurious Interrupt Vector
+  LAPIC_ISR = 0x0100,   // Interrupt Status (8 registers)
+  LAPIC_TMR = 0x0180,   // Trigger Mode (8 registers)
+  LAPIC_IRR = 0x0200,   // Interrupt Request (8 registers)
+  LAPIC_ESR = 0x0280,   // Error Status
+  LAPIC_ICRLO = 0x0300, // Interrupt Command
+  LAPIC_ICRHI = 0x0310, // Interrupt Command [63:32]
+  LAPIC_TIMER = 0x0320, // Local Vector Table 0 (TIMER)
+  LAPIC_PCINT = 0x0340, // Performance Counter LVT
+  LAPIC_LINT0 = 0x0350, // Local Vector Table 1 (LINT0)
+  LAPIC_LINT1 = 0x0360, // Local Vector Table 2 (LINT1)
+  LAPIC_ERROR = 0x0370, // Local Vector Table 3 (ERROR)
+  LAPIC_TICR = 0x0380,  // Timer Initial Count
+  LAPIC_TCCR = 0x0390,  // Timer Current Count
+  LAPIC_TDCR = 0x03E0,  // Timer Divide Configuration
 };
 
-enum {					// LAPIC_SVR
-  LAPIC_ENABLE	= 0x00000100,	// Unit Enable
-  LAPIC_FOCUS	= 0x00000200,	// Focus Processor Checking Disable
+enum {  // LAPIC_SVR
+  LAPIC_ENABLE  = 0x00000100,   // Unit Enable
+  LAPIC_FOCUS   = 0x00000200,   // Focus Processor Checking Disable
 };
 
-enum {					// LAPIC_ICRLO
-					// [14] IPI Trigger Mode Level (RW)
-  LAPIC_DEASSERT = 0x00000000,	// Deassert level-sensitive interrupt
-  LAPIC_ASSERT	= 0x00004000,	// Assert level-sensitive interrupt
+enum {  // LAPIC_ICRLO
+  // [14] IPI Trigger Mode Level (RW)
+  LAPIC_DEASSERT = 0x00000000,  // Deassert level-sensitive interrupt
+  LAPIC_ASSERT  = 0x00004000,   // Assert level-sensitive interrupt
 
   // [17:16] Remote Read Status
-  LAPIC_INVALID	= 0x00000000,	// Invalid
-  LAPIC_WAIT	= 0x00010000,	// In-Progress
-  LAPIC_VALID	= 0x00020000,	// Valid
+  LAPIC_INVALID = 0x00000000,   // Invalid
+  LAPIC_WAIT    = 0x00010000,   // In-Progress
+  LAPIC_VALID   = 0x00020000,   // Valid
 
   // [19:18] Destination Shorthand
-  LAPIC_FIELD	= 0x00000000,	// No shorthand
-  LAPIC_SELF	= 0x00040000,	// Self is single destination
-  LAPIC_ALLINC	= 0x00080000,	// All including self
-  LAPIC_ALLEXC	= 0x000C0000,	// All Excluding self
+  LAPIC_FIELD   = 0x00000000,   // No shorthand
+  LAPIC_SELF    = 0x00040000,   // Self is single destination
+  LAPIC_ALLINC  = 0x00080000,   // All including self
+  LAPIC_ALLEXC  = 0x000C0000,   // All Excluding self
 };
 
-enum {					// LAPIC_ESR
-  LAPIC_SENDCS	= 0x00000001,	// Send CS Error
-  LAPIC_RCVCS	= 0x00000002,	// Receive CS Error
-  LAPIC_SENDACCEPT = 0x00000004,	// Send Accept Error
-  LAPIC_RCVACCEPT = 0x00000008,	// Receive Accept Error
-  LAPIC_SENDVECTOR = 0x00000020,	// Send Illegal Vector
-  LAPIC_RCVVECTOR = 0x00000040,	// Receive Illegal Vector
-  LAPIC_REGISTER = 0x00000080,	// Illegal Register Address
+enum {  // LAPIC_ESR
+  LAPIC_SENDCS  = 0x00000001,     // Send CS Error
+  LAPIC_RCVCS   = 0x00000002,     // Receive CS Error
+  LAPIC_SENDACCEPT = 0x00000004,  // Send Accept Error
+  LAPIC_RCVACCEPT = 0x00000008,   // Receive Accept Error
+  LAPIC_SENDVECTOR = 0x00000020,  // Send Illegal Vector
+  LAPIC_RCVVECTOR = 0x00000040,   // Receive Illegal Vector
+  LAPIC_REGISTER = 0x00000080,    // Illegal Register Address
 };
 
-enum {					// LAPIC_TIMER
-					// [17] Timer Mode (RW)
-  LAPIC_ONESHOT	= 0x00000000,	// One-shot
-  LAPIC_PERIODIC = 0x00020000,	// Periodic
+enum {  // LAPIC_TIMER
+  // [17] Timer Mode (RW)
+  LAPIC_ONESHOT = 0x00000000,   // One-shot
+  LAPIC_PERIODIC = 0x00020000,  // Periodic
 
   // [19:18] Timer Base (RW)
-  LAPIC_CLKIN	= 0x00000000,	// use CLKIN as input
-  LAPIC_TMBASE	= 0x00040000,	// use TMBASE
-  LAPIC_DIVIDER	= 0x00080000,	// use output of the divider
+  LAPIC_CLKIN   = 0x00000000,   // use CLKIN as input
+  LAPIC_TMBASE  = 0x00040000,   // use TMBASE
+  LAPIC_DIVIDER = 0x00080000,   // use output of the divider
 };
 
-enum {					// LAPIC_TDCR
-  LAPIC_X2 = 0x00000000,	// divide by 2
-  LAPIC_X4 = 0x00000001,	// divide by 4
-  LAPIC_X8 = 0x00000002,	// divide by 8
-  LAPIC_X16 = 0x00000003,	// divide by 16
-  LAPIC_X32 = 0x00000008,	// divide by 32
-  LAPIC_X64 = 0x00000009,	// divide by 64
-  LAPIC_X128 = 0x0000000A,	// divide by 128
-  LAPIC_X1 = 0x0000000B,	// divide by 1
+enum {  // LAPIC_TDCR
+  LAPIC_X2 = 0x00000000,        // divide by 2
+  LAPIC_X4 = 0x00000001,        // divide by 4
+  LAPIC_X8 = 0x00000002,        // divide by 8
+  LAPIC_X16 = 0x00000003,       // divide by 16
+  LAPIC_X32 = 0x00000008,       // divide by 32
+  LAPIC_X64 = 0x00000009,       // divide by 64
+  LAPIC_X128 = 0x0000000A,      // divide by 128
+  LAPIC_X1 = 0x0000000B,        // divide by 1
 };
 
 uint *lapicaddr;